1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a data output timing control circuit.
2. Related Art
A semiconductor apparatus is configured to operate through a clock synchronous system to match the operation timing and ensure much faster operation without occurrence of errors. If an external clock is used inside the semiconductor apparatus, time delay (clock skew) due to an internal circuit occurs in output data. Accordingly, a delay locked loop is provided to generate a DLL clock includes a compensation for a model delay value tREF that is obtained by modeling a delay amount of an internal circuit of the semiconductor apparatus, that is, a path through which data is output. By using the DLL clock in the semiconductor apparatus, data can be output outside the semiconductor apparatus in synchronization with the external clock.
On the other hand, in the semiconductor apparatus, a time point when data is output outside the semiconductor apparatus is determined in accordance with data output delay information (CAS latency) during a read operation. The data output delay information indicates a number of clock cycles after which first data is output after receiving an external read command which is input based on an external clock. A data output timing control circuit is a circuit that is separately provided inside the semiconductor apparatus so that data can be output to match the data output delay information.
The purpose of the data output timing control circuit is to output the first data to the outside at a rising edge of the set external clock, and for this, the data output timing control circuit generates an output enable flag signal for controlling the data output time. The output enable flag signal is an internal signal of the semiconductor apparatus which is synchronized with the DLL clock.
FIG. 1 is a block diagram of a data output timing control circuit in the related art.
The data output timing control circuit of the related art shown in FIG. 1 includes a delay locked loop 10, a delay amount calculation unit 20, and a phase adjustment unit 30.
The delay locked loop 10 is configured to receive the external clock EXTCLK, and generate a DLL clock DLLCLK through delay of the external clock for n*tCK−tREP (where n is a natural number, and tCK may be one clock cycle) to compensate for another model delay value tREP, which may be a replica delay time. Specifically, the delay locked loop 10 includes a variable delay unit 11 configured to adjust a delay amount of the external clock EXTCLK (as a result, the delay amount is adjusted to n*tCK−tREP) in response to a phase detection signal PDET, a delay model unit 12 configured to delay the DLL clock DLLCLK for the model delay value tREF and generate a feedback clock FBCLK, and a phase comparison unit 13 configured to compare phases of the external clock EXTCLK and the feedback clock FBCLK and generate the phase detection sign PDET.
The delay amount calculation unit 20 is configured to subtract a code value of a counting code N, which is obtained by counting the delay amount (n*tCK−tREP)+(tREP), that is, n*tCK, of an output reset pulse signal OERST based on the external clock EXTCLK, from a code value of data output delay information CL and output the result of subtraction as a delay control code CL−N. Specifically, the delay amount calculation unit 20 includes a variable delay unit 21 configured to delay the output reset pulse signal OERST for n*tCK−tREP and a delay model unit 22 configured to delay the output reset pulse signal OERST for tREP in response to the phase detection signal PDET (the variable delay unit 21 and the delay model unit 22 may comprise a reset pulse delay unit, and the output signal of the reset pulse delay unit is defined as a delayed output reset pulse signal DOERST). The delay amount calculation unit 20 may also include a counter unit 23 configured to start counting in response to the output reset pulse signal OERST, finish the counting in response to the delayed output reset pulse signal DOERST in synchronization with the external clock EXTCLK, and generate a counting code N. Still further, the delay amount calculation unit 20 may also include a calculation unit 24 configured to subtract the code value of the counting code N from the code value having the data output delay information CL and output the result of subtraction as the delay control code CL−N.
The phase adjustment unit 30 is configured to receive and delay an internal read command IRDCMD for n*tCK−tREP, adjust the phase as many as the number of clocks of the DLL clock DLLCLK that corresponds to the delay control code CL−N, and output the phase-adjusted signal as an output enable flag signal OEFLAG. Specifically, the phase adjustment unit 30 includes a command receiver 31 configured to receive the external read command RD and generate an internal read command (hereinafter referred to as a “read command”) IRDCMD, a variable delay unit 32 configured to delay the read command IRDCMD for n*tCK−tREP in response to the phase detection signal PDET and output the result of delay as a delayed read command DRDCMD, and a shift register 33 configured to adjust the phase of the delayed read command DRDCMD as many as the number of clocks of the DLL clock DLLCLK that corresponds to the delay control code CL−N.
As a result, the data output timing control circuit activates the output enable flag signal when the read command IRDCMD is delayed for (n*tCK−tREP)+(CL−N), that is, CL−tREF. The data is output to the outside when the data output path delay time tREP elapses after the output enable flag signal OEFLAG is activated, that is, when the time that is accurately as long as the data output delay information elapses after the external read command RD is applied.
FIGS. 2A and 2B are diagrams showing signal waveforms of the phase adjustment unit 30.
FIG. 2A is a signal waveform diagram of the phase adjustment unit 30 that is normally operated. The external read command RD is applied through the command receiver 31 in synchronization with the external clock EXTCLK, but the read command IRDCMD that is internally used is a signal that is actually delayed for an amount as large as the internal delay amount. The variable delay unit 32 delays the read command for n*tCK−tREP.
Thereafter, the shift register 33 shifts the delayed read command DRDCMD in synchronization with the DLL clock DLLCLK. At this time, the delayed read command DRDCMD has a setup margin as large as A.
On the other hand, the clock frequency of the semiconductor apparatus is an index that indicates the data processing speed of the semiconductor apparatus, and modern technology has been developed in the direction in which the clock frequency gradually increases. FIG. 2B is a signal waveform diagram of an output timing control circuit of a semiconductor memory apparatus that uses a higher clock frequency than the signals shown in FIG. 2A.
FIG. 2B is a signal waveform diagram of the phase adjustment unit 30 of the output timing control circuit that uses a higher external clock frequency. FIG. 2B shows an example where the phase adjustment unit 30 may malfunction due to the high clock frequency.
As shown in FIG. 2A, the external read command RD is applied through the command receiver 31 in synchronization with the external clock EXTCLK, but the read command IRDCMD that is internally used is a signal that is actually delayed as large as the internal delay amount. The internal delay amount is equal to the value in FIG. 2A, but in this embodiment, it may be a relatively large value since the clock period is short. The variable delay unit 32 delays the read command IRDCMD for n*tCK−tREP.
Thereafter, the shift register 33 must shift the delayed read command DRDCMD in synchronization with the DLL clock DLLCLK, and in this case, since the delayed read command DRDCMD is generated to exceed the setup margin for a time period as large as B, the shift register 33 operates in synchronization with the DLL clock DLLCLK that is one period later than the set timing. Accordingly, the output enable flag signal OEFLAG is activated at a time point that is one period later than the set time point, and the data is output to the outside at a time point that is one period delayed from the set data output delay information CL. This causes malfunction of the whole semiconductor apparatus.